● Design of Delay Locked Loops, and digital logic in 14nm cmos circuits
● Layout of circuitry in Finfet Technology.
○ Responsible for design, layout, testing, extraction, and verification of mixed signal blocks
in submicron and deep submicron cmos.
○ Single and multi-staged comparators sampling circuits and amplifiers
○ Noise simulation of ADC Chain (PSS and Time Domain)
○ Programmable on chip DACs and reference generators
● Image Sensor Full Chip Verification:
○ AMS Modeling of all blocks including ADC sub blocks and control circuits
○ Verification of chip bringup, SPI read write, data readout and gross timing
○ Verification of various modes of operation.
● High Speed Data Transmitters:
○ Multi GHz range PLL with data serializer of up to 4GBPS silicon verified
○ Multi GHz range PLL with programmable data serializer of 1 to 5 GBPS, not silicon verified
○ Performed PSS and Noise simulations to optimize noise per components of PLL and serializer
○ Performed Time Domain Noise simulations, results match laboratory measurements
○ Writing verilog for testing PLL and transmitter data capturing with Xillinx GTX IO blocks
● Design of cmos digital blocks used in cooled and uncooled large format infrared ROICs:
high speed counters, synchronization circuits, analog interface circuitry (LVDS, RSDS),
comparators, and level shifters and Low Dropout (LDO) power circuit
● Design of digital architecture, gate level logic, test circuitry, current sources,
and analog interfacing blocks. Performed behavioral logic simulation,
transistor level spice simulation, layout, DRC, LVS, parasitic extraction, and characterization
● Documentation and creation of manuals, and presentations to discuss specifications
and operation of design, and interfacing with customers
architecture in a multi clock domain environment with Verilog RTL.
● Timing and functional verification of RTL.
● Analog and All Digital PLLs
● High Bandwidth DACs and ADCs
● High Precision DACs and ADCs
● Large Array Imagers
● Bandgaps and Reference Generators
● Digital and Analog Delta Sigma Modulation
● RF applications (Details by request)
● Extreme Environment Applications
Tools:
● Cadence: Virtuoso, ADEXL, layout and simulation
● Silicon Layout verification with Calibre
● Working with laboratory equipment and debugging of silicon
● Verilog and AMS Modeling
● Perl + Python scripting